1. Field of the Invention
The present invention relates to an integrated circuit chip identification method and more particularly to an integrated circuit chip identification method adapted for use with a Level Sensitive Scan Design (LSSD) system and testing technique of the type disclosed and defined in U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and 4,268,902 and of common assignee and other scan design methodologies.
2. Description of the Prior Art
Due to the complexity and the extremely great number of circuit functions contained on a single large scale integrated (LSI) device or chip, the LSSD system and testing technique has been widely used. LSSD requires that all latches be connected together in a shift register or scan ring for testing and this methodology allows patterns to be shifted (scanned) into and out of all latches in the design.
U.S. Pat. No. 4,268,903 issued May 19, 1981 and of common assignee discloses the LSSD system and testing technique and a computer system including a maintenance interface compatible with LSSD design for synchronizing the operation of a service processor and a central processing unit. The disclosure of U.S. Pat. No. 4,268,902 is incorporated herein by reference.
U.S. Pat. Nos. 4,293,919, 4,298,980 and 4,493,077 provide examples of LSI circuitry generally conforming to LSSD system rules and scan ring testing methods.
U.S. Pat. No. 4,519,078 discloses a method of self-testing LSI circuits that incorporates internally generated pseudorandom sequences as test vectors to stimulate the logic circuits under test. Responses inside the chip to the test vectors are analyzed by internal or external signature analysis to determine if the circuit has functioned properly.
U.S. Pat. No. 4,710,931 discloses a test partitionable logic circuit including a plurality of functional modules. Each of the functional modules is addressable through an address decode/select circuit to operationally isolate the select modules and define a test boundary so that a separate test pattern can be generated for each module and each module can be tested separate from each other module, reducing both the time to complete a total test of the system and also the time for generating the test pattern.
An accurate chip identification is needed to facilitate self-test data selection because the exact logic structure of a particular chip is required for proper self-test data selection. Small changes in the logic structure in a chip that do not affect the microcode loads cause failures in self-testing. However, no mention of any mechanism for chip identification is provided by the above patents.
Japanese patent application publication No. 58-3252 discloses an LSI chip having an identification code pattern representing the logic structure of an IC formed in the LSI chip. A set of external pins or terminals are provided with the LSI chip for reading the identification code pattern from the LSI chip in parallel form. While the identification code pattern formed in the chip facilitates automated testing, this approach is not practical due to the required external terminals that must be provided to access the identification code pattern. The number of bits that can be used to define the identification code pattern is limited by the number of external terminals available for the chip.